1. Field of the Invention
The present invention relates to a solid state imaging apparatus and to a method for handling a region to be read that permit a pixel in a desired region to be read.
Priority is claimed on Japanese Patent Application No. 2004-112042, filed Apr. 6, 2004, the content of which is incorporated herein by reference.
2. Description of Related Art
A conventional solid state imaging apparatus that permits a pixel in a desired region to be read is known. In such a solid state imaging apparatus, in order to allow only a desired region to be read, an electric potential storage portion is provided to each of the shift register unit portions that construct a horizontal scanning circuit and a vertical scanning circuit. An example of such a construction is shown in FIG. 17. In FIG. 17, reference numeral 1 denotes a shift register unit having a first clock-type inverter 1-1 and a second clock-type inverter 1-2 that are serially connected, reference numeral 2 denotes a storage portion having a first inverter 2-1 and a second inverter 2-2 that are serially connected, reference numeral 3 denotes a storage switch that conveys a level of the shift register unit 1 to the storage portion 2, and reference numeral 4 denotes a transfer switch that conveys information stored in the storage portion 2 to the shift register unit 1.
One terminal of the storage switch 3 is connected to an output of a first clock-type inverter 1-1 of the next stage shift register, and the other terminal is connected to an input of a first inverter 2-1 of the storage portion 2. One terminal of the transfer switch 4 is connected to an output of a first clock-type inverter 1-1, and the other terminal is connected to an input of a second inverter 2-2 of the storage portion 2. Reference numeral 5 represents a unit stage of the shift register. Although a 7-stage shift register is shown in FIG. 17, an actual solid state imaging apparatus has more numeral stages. It should be understood that the final stage has no storage portion 2.
The first clock-type inverter 1-1 is activated in response to a driving clock φ2 being set to an “H” level, and the second clock-type inverter 1-2 is activated in response to a clock φ1 being set to an “H” level. The first stage shift register unit 1 inputs a start pulse φST. The storage switch 3 is turned on in response to a memory pulse φM being set to an “H” level, and the transfer switch 4 is turned on in response to a transfer pulse φT being set to an “H” level.
The operation of the shift register that has the above-described configuration will be described with reference to a timing chart shown in FIG. 18. First, in a pre-scanning that is executed prior to an actual scanning, the start pulse φST is set to an “H” level at the time T1, and signals stored within the shift registers are shifted in response to clocks φ1 and φ2. At the time T2, a memory pulse φM is set to an “H” level, and each of the levels at nodes SR1.5, SR2.5, . . . , and SR6.5 within each of the shift register units 1 is stored in a respective storage portion 2 at that time in response.
Since a storage portion 2 is connected to a shift register unit of the next stage, a level that is stored in the input of the storage portion 2 in each of the shift register stages is a “L” level except a storage portion 2 of the third stage shift register that stores an “H” level.
Next, at the time T3, a transfer pulse φT is set to an “H” level, and the respective level stored during the time T2 is transferred to the nodes SR0.5, SR1.5, . . . , and SR5.5 within each of the shift register unit 1 in response. Since the node SR6.5 in the last stage retains the previous level since no transfer switch 4 is connected to the node SR6.5 of the last stage. In this case, since the clock φ1 is set to an “H” level, inverted outputs in the nodes SR0.5, SR1.5, . . . , and SR6.5 are output to the nodes SR1.0, SR2.0, . . . , and SR7.0 in each of the shift register units 1. A shift operation is started according φ1 and φ2, and a scanning of the shift registers are started beginning from SR3.0.
Furthermore, when the memory pulse φM is set to an “H” level at the time T4, similar to the pre-scanning time period, each of the levels at nodes SR1.5, SR2.5, . . . , and SR6.5 in each of the shift register unit 1 is stored in a respective storage portion 2, and accordingly the output of each of the storage portions 2 stores the same level as that at the time T2. At the time T5, in response to the transfer pulse φT being set to an “H” level, information stored in the storage portions 2 is transferred so that scanning of the shift registers is started beginning at SR3.0, as at the time T3. Again, a storing operation of the scanning start position is started at the time T6.
Thus, in the actual scanning time period starting from the time T3, scanning of the shift registers is started from the node SR3.0 by transferring the information stored in the storage portion 2. The starting position of the actual scanning can be changed by changing the timing to set the signal φM to high, thus, a desired region can be read.
However, the above-identified technique does not specify any driving method or means to change a region to be read during a read operation of the solid-state image sensing device. Furthermore, in the above-identified technique, since a pre-scanning is required for reading a desired region, picture signals may be interrupted if a read region is changed while the solid-state image sensing device is executing a read operation.